Most modern electronic devices include at least some digital circuits. Technological advances have vastly increased the available processing power and memory density, while lowering the cost of both. While data-handling and computational circuits are naturally digital, even electronic circuits that were traditionally primarily analog—such as communication devices, signal processing circuits, control systems, and the like—are now often primarily digital, with analog-to-digital conversion (ADC) at the input, and digital-to-analog conversion (DAC) at the output.
As one representative, non-limiting example, consider a modern mobile wireless telecommunication device (e.g., smartphone), also known in the art as User Equipment (UE). Radio frequency signals received at an antenna may be amplified, filtered, and frequency downconverted by analog circuts, and are then converted to the digital domain. Many of the signal processing tasks—such as demodulation, data decoding, decryption, and the like—are performed digitally. The received digital data is processed by application programs, and may be converted to the analog domain and rendered to a speaker or display. Additionally, the device may receive analog signals from a microphone or camera, convert the signals to the digital domain, and perform inverse signal processing operations prior to generating analog RF signals, which are transmitted to the network. Similar RF signal processing tasks occur in the base station, also known as an eNodeB, of a wireless communication network—i.e., analog RF signals received at one or more antennas may be processed by analog circuits, and are then digitized for further processing, storage, transmission, and the like.
Increasingly high bandwidth and data rates (e.g., for 5G networks) impose the requirements of very high speed and accuracy in analog to digital data conversion. One known approach to improving ADC—at the cost of system complexity and power consumption—is time interleaving. In this approach, a number of lower-frequency sub-ADC circuits convert an analog input, and their outputs are combined at a higher sampling rate, to obtain the desired throughput.
FIG. 1 depicts the concept of time-interleaved ADC. A continuous time signal x(t) is converted to a digital signal y(n) using N sub-ADCs. Each sub-ADC converts the data to a sampling frequency 1/N that of the digital output y(n).
FIG. 2 shows a conventional circuit used to implement the time-interleaved ADC concept of FIG. 1. Each sub-ADC comprises a channel and a sampling input circuit. The sampling input circuit is represented with an ideal switch and a sampling capacitance. An input signal Vin is rotated through the sub-ADCs by actuating the switches using successive clock signals CK1 . . . CKN. The digital outputs of each sub-ADC are multiplexed to yield the digital output Dout. A clock circuit such as a Phase Locked Loop (PLL) or Digital Locked Loop (DLL) generates the clock signals.
A known limitation of ADC implementation is the Signal to Noise and Distortion Ratio (SNDR) that can be obtained, due to nonlinearity of the sampling switches. To achieve high resolution (e.g., 9 bits or more), the sampling switch must be linearized. One known approach to linearize a switch is to drive the gate of a transistor with a higher voltage that depends on the input signal, to approach a constant (signal independent) on-resistance. For example, if a sampling switch transistor receives a gate voltage of VDD Vin and an input signal foltage at the source of Vin, then the gate-to-source voltage Vgs is Vg−Vs=(VDD+Vin)−Vin=VDD. This technique is known as bootstrapping. See, e.g., Marcel Pelgrom, Analog-to-Digital Conversion, §4.3.4 CMOS Bootstrap Techniques (Springer Science & Business Media, 2012), the disclosure of which is incorporated herein by reference. Bootstrap circuits solve two problems associated with a one-transistor switch: the limited input range due to the threshold voltage, and the switch resistance variation. Bootstrap circuits improve performance in both respects by increasing the effective drive voltage beyond the power supply limits.
FIG. 3 depicts a sub-ADC with a bootstrapped sampling switch. The switch M11 samples the Voltage Vin applied to the capacitor (CS in FIG. 2). During a first half-period of the clock signal, when Clk is high, both M7 and M10 are turned on, charging the capacitor to VDD, while M8 isolates the capacitor from the rest of the circuit, and M12 turns off switches M9 and M11. During the second half-period, when Clk is low, the capacitor is isolated from the power supply, and connected via M8 to the shared gate nodes of M9 and M11, which are isolated from ground by M12. This turns M9 and M11 on, connecting the input voltage Vin to the capacitor and presenting their sum at the output Vout. The circuit thus operates over one complete period of the Clk signal—charging the capacitor in a first half-period, and sampling the input by adding it to VDD on the capacitor in a second half-period.
For each sampling switch M11, four equivalent transistor gate terminals (M7, M10, M12, and M8) must be driven by the clock generation circuits. A clock boosting circuit, such as a “boost” charge pump, drives the clock signal into the gate of switch M7 with a voltage that is greater than the power supply voltage. This is necessary to turn the gate “on”—that is, the gate voltage must be higher (by at least a threshold voltage Vth) than the voltage at its source, which is VDD. Additionally, as described above, relating the excess voltage applied to the gate to the input voltage improves the linearity of the switch. The charge pump, of course, requires additional circuitry and increases power consumption.
FIG. 4 depicts a similar solution that does not require a charge pump to generate a bootstrap voltage in excess of the power supply. In this case, the input voltage Vin is added to the power supply voltage, and the sum is applied to the gate of M7. Note that M7 is a PMOS device, as opposed to the NMOS device depicted in FIG. 3, since in this case when Clk is high, M12 drives the gate of M7 to ground. Otherwise, the circuit operates similarly to that described above. In this implementation, three gates must be driven (M10, M12, and M8). Although a charge pump is not necessary to boost the drive on M7, the switches M8 and M9, as well as the bootstrap capacitance, must increase in size to achieve the same SNDR as the implementation depicted in FIG. 4, thus reducing the area advantage of omitting the charge pump.
In many applications, improved performance, stability, linearity, and noise immunity are achieved by implementing circuits in a differential configuration. That is, rather than representing a signal value as a single voltage referenced to ground, the circuit is configured as mirror-image positive and negative sub-circuits, and the signal value is represented as the difference of two voltages. As used herein, with respect to differential circuits, the terms “positive” and “negative” are terms of reference used to identify the two complimentary halfs of a differential circuit, or the dual inputs or outputs (e.g., “positive input” or “negative output”). The terms do not indicate any value of, e.g., a voltage with respect to zero volts. If the sample and hold circuit of either FIG. 3 or 4 is implemented in a differential configuration, the circuit will be replicated to implement the positive and negative sub-circuits, and twice the capacitance must be driven. Thus, eight switches (FIG. 3) or six switches (FIG. 4) must be driven for each different sample and hold circuit. These numbers must then be multiplied by N, where N is the number of sub-ADCs in the time-interleaved ADC. Hence the total number of devices to be driven is 8N or 6N.
Additionally, such a large number of gates interconnections complicate the clock distribution required by introducing delays and imperfections. These require additional calibration circuitry to retime each sub-ADC. Conventional bootstrap ADC sub-circuits for a time-interleaved ADC thus suffer high gate count (8N or 6N), have complicated clock distribution and operation challenges, and consume large silicon area.
The Background section of this document is provided to place embodiments of the present invention in technological and operational context, to assist those of skill in the art in understanding their scope and utility. Unless explicitly identified as such, no statement herein is admitted to be prior art merely by its inclusion in the Background section.